Method and apparatus for driving reflective bistable cholesteric displays

ABSTRACT

This invention provides a method and apparatus for driving bistable cholesteric liquid crystal displays. The method and apparatus provided a display in which all the pixels are initially driven to the P state. Selected pixels for the display are then driven to the FC state to provide the desired message. The state of the pixels is then maintained for a viewing period prior to any resetting of the display to the P state. The switching from the P state to the FC state allows faster addressing times and lower voltages to be used in driving the display.

BACKGROUND

1. Field of the Invention

This invention relates to bistable cholesteric displays and, inparticular, although not necessarily solely, a method and apparatus fordriving reflective bistable cholesteric displays.

2. Description of the Prior Art

Bistable cholesteric liquid crystal displays “BCD” are already wellknown and utilized in a number of applications. The bistable cholestericdisplay usually consists of two pieces of glass forming a thin liquidcrystal cell. The liquid crystal material is usually composed of twistednematic liquid crystal heavily doped with a chiral dopant to give theliquid crystal a strong twist sense or chirality. Such cholestericliquid crystal displays exhibit two stable states at a zero drivingvoltage. The first of these is the reflective planar “P” state and, asthe name suggests, is reflective in normal usage. The second state isthe scattering/transparent focal conic (FC) state. In normal usage, theFC state is transparent.

When used in conjuntion with a dark light absorber placed at the back ofthe display, the FC state will appear black and the P state would appearto be bright when the display is viewed in reflection. The colour of thebright state can be adjusted by varying the chirality and pitch of theliquid crystal material. Such bistable liquid crystal displays arediscussed in literature such as the monograph by S. Chandrasekharentitled “Liquid Crystals” (Cambridge University Press, 1977).

A number of schemes have been developed to drive such bistable displaysin a passive matrix manner. U.S. Pat. No. 4,571,585 by Stein et al.utilizes a wave form applied to the individual pixels which has beenspecially tailored in order to avoid cross talk problems. A number ofvoltage levels are needed for matrix driving of the display making theinvention rather cumbersome. An alternative matrix driving scheme isdisclosed in the document entitled “A High Information ContentReflective Cholesteric Display” (SID 95 Digest, 1995) by Per et al. Inthis scheme, commercial LCD driver chips were used and the display wasscanned with 20 ms pulses. An upper voltage of 41 V would give the Pstate and a lower voltage of 33 V would produce the FC state. Thescanning speed of 20 ms per line was achieved. However, this scheme hasthe disadvantage of a high voltage requirement and the relative slownessin scanning.

A more complicated dynamic driving scheme is discussed in the documententitled “Cholesteric Reflective Display: Drive Scheme and Contrast”(Appl. Phys. Lett., 64, 1905, 1994) by Yang et al. In this scheme, a 1ms addressing time was shown to be possible although was only providedat the expense of more complicated wave forms and driver electronics.Again, the voltages required were quite high at greater than 40 V.

A further drawback in the dynamic scheme of Yang et al. is theappearance of a dark band in the display. A yet further disadvantage isthat the image does not appear instataneously instead, there is a 300 msdelay due to the slow switching from the FC state to the P state. A yetfurther disadvantage is that the contrast ratio of the dynamic drivingscheme is very sensitive to the amplitude of the evolution voltage, The1 ms addressing time shown to be possible at the expense of morecomplicated electronics is discussed in documents entitled “DynamicDrive for Bistable Reflective Cholesteric Displays: A Rapid AddressingScheme (SID 95 Digest, p.347, 1995) and “High Performance Dynamic DriveScheme for Bistable Reflective Cholesteric Displays” (SID 96 Digest,p.359, 1996).

Faster switching to the P state has been demonstrated recently in aspecially aligned BCD discussed in the document by M. H. Lu (Journal ofApplied Physics, 81, 1063, 1997). Even with this faster switchingavailable with a specially aligned BCD, it still takes approximately 10ms for the switching.

OBJECT OF THE INVENTION

It is an object of the present invention to provide a method andapparatus for the driving of a bistable cholesteric liquid crystaldisplay that can utilize simpler clerical wave forms and is capable offaster line addressing speed to overcome some of the disadvantages ofthe prior art or at least provide the public with a useful choice,

SUMMARY OF THE INVENTION

The present invention provides a method of driving a bistablecholesteric liquid crystal display comprising setting the displayinitially to the P state. Once the liquid crystal display has completelyswitched to the P state, the ere panel is scanned line by line in thesame manner as in conventional passive matrix super twisted nematic LCDsto switch the selected pixels from the P state to the FC state. Thenon-selected pixels are allowed to remain in the P state.

The present invention also provides a bistable cholesteric liquidcrystal display driven in tis manner. The driver provides an initialpulse or pulse train to set or reset the display to the P state. Thedisplay contains a matrix of overlapping electrodes such that one set ofelectrodes may be driven by an address pulse and the second set ofelectrodes in the display driven w data pulses. The pixels defied by theoverlapping regions between the two sets of electrodes are switched bythe selected pixels receiving a: address pulse and data pulse which arecumulative while the non-selected pixels receive a voltage of theaddress pulse is the data pulse. Selection of the voltages are chosensuch that the selected pixels will switch from the P state to the FCstate and the non-selected pixels will red in the P state.

In a final stage of the driving cycle, the display is allowed to staywithout any driving voltages applied. This is the viewing phase of thedriving scheme.

Further aspects of the invention may be considered novel when consideredby those skill in the art to which the invention relates.

BRIEF DESCRIPTION OF THE DRAWINGS

The pried embodiments of the invention will now be discussed withreference to the following drawings in which:

FIG. 1 shows a plot of the reflectance of a BCD cell against the voltageof the switching pulse;

FIG. 2 provides a plot of the switching voltage against time to show theswitching of the BCD from the P state to the FC state;

FIG. 3 is a plot showing the switching history between the P and FCstates in an example of the invention;

FIG. 4 shows an example of the timing sequence of a driving scheme inaccordance with this invention;

FIG. 5 is a plot showing the influence of the non-selection pulse rainon the P state pixel;

FIG. 6 is a cross sectional view through the basic structure of a liquidcrystal display in accordance with one embodiment of the invention and,

FIG. 7 shows an electrode pattern for inclusion in a BCD cell inaccordance with a preferred embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The invention will now be described with reference to preferredembodiment and experimental embodiments.

This invention seeks to provide a driving method and apparatus forbistable cholesteric liquid crystal displays. The invention is based onthe observation that whereas switching from the FC state to the P stateof the cholesteric liquid crystal display takes 0.3 s, switching fromthe P state to the FC state can take less than 1 ms.

A preferred embodiment of the driving scheme sets the whole LCD panel tothe P state by the application of either a single pulse or a pulse trainwith a duration of T_(r) and an amplitude of V_(r). This is referred toas the reset pulse. Typically, T_(r) can be 20 ms and V_(r) can be 40 V.

A time T_(p) is allowed for the liquid crystal display to complete theswitch to the P state, The entire LCD panel may then be scanned line byline in the same manner as conventional passive matrix super twistednematic LCDs. Such LCDs typically provide a matrix of electrodes whichare generally provided as two sets of substantially orthogonalelectrodes. These will be referred to as horizontal address lines orhorizontal rows and vertical data lines or vertical columns in thesubsequent description. Of course, the exact arrangement of theelectrodes may be varied in accordance with alternative structureswithout departing from the general application of the invention. Theterms “horizontal” and “vertical” are used for convenience to refer tothe different substantially perpendicular sets of electrodes in thepreferred embodiment. They are not intended as a restriction to thespacial arrangement or alignment of the electrodes or the displayitself.

In the preferred embodiment, the horizontal address lines are driven byaddress pulses of amplitude V_(g), and a duration of T_(g). The verticaldata lines are driven with data pulses of amplitude ±V_(d) and durationT_(g). The pixels in the display are provided by the overlapping regionsof the electrodes. The selected pixels for the display are subjected toa voltage of V_(g)+V_(d) while the non-selected pixels will receive avoltage of V_(g)-V_(d). Selection of the values of V_(a) and V_(d) maybe chosen such that the selected pixels are switched from the P state tothe FC state on receiving the total of the voltages and the non-selectedpixels are allowed to remain below the threshold in the P state.

The display may then be allowed to stay without any driving voltagesapplied. This is the viewing phase of the driving scheme. The viewingduration can be of any length and the viewing time may be periodic orirregular in duration.

Thus, in the overall driving scheme to refresh the display in the BCD inthe preferred embodiment, there are three stages. The display may berefreshed or reset, subsequently scanned and the final stage is theviewing of the display.

It is observed that addressing time of T_(g) of less than 1 ms per lineis possible in a preferred embodiment. Such addressing time per line isalready good enough for many applications such as the displays inpagers, cellular phones, personal data banks, etc, Even for a 100 linedisplay panel, the total writing time is only 0.1 s at such anaddressing speed. Furthermore, the scanning and data voltages may bekept quite low. In a preferred embodiment, the voltages V_(g) and V_(d)are 24 V and 6 V respectively. Such low voltages can be provided bycommercial super twisted nematic liquid crystal display drivers.

In the preferred embodiments, the reset voltage V_(r) may be the maximumhigh voltage required. This may generally fall in the range of 40 V to25 V depending on the reset pulse duration required. For a 40 V resetpulse, the reset pulse duration can be as small as 10 ms. For a 25 Vreset pulse, the reset pulse duration has to be somewhat longer.Furthermore, as the reset pulse need not be applied all to oneelectrode, it can be shared between the row and column or horizontal andvertical electrodes in order to reduce the voltage requirement. Forapplications which do not require frequent or fast resetting, the lowervoltage may be preferred.

EXPERIMENTAL DATA AND EXAMPLES

To implement the method in a preferred embodiment, a low voltage cellhas to be made. Several test cells were made. In a particular preferredembodiment, the cell gap of the sample LCD cell was 5 μm. The liquidcrystal was provided with a homogeneous alignment and a mixture of achiral dopant and ZLI 6204 were used in the sample cells. Although theseare provided in the preferred embodiment, other nematic liquid crystalscan also be used.

The response of the BCD cell to pulses of various voltages was measuredusing the following procedure. First the cell was driven to thereflective P state by a refresh pulse. The stabilized reflectance of thecell was measured as a function of the voltage of a switching pulse.This procedure was repeated with the cell in the FC state initially.Both the width of the applied switching pulse and the refresh pulse were10 ms in this measurement, The pulse duration was changed in othermeasurements taken.

In this particular experiment, the central wave length of the incidentlight sources was 514 nm. The pitch of the BCD cell was adjusted tomatch that accordingly. As a result, the incident light is nearperpendicular to the cell surface.

The results of this experiment are shown in FIG. 1. It can be seen thatthe curve P-FC-P represents the response of the cell originally in the Pstate prior to the application of the switching pulse. It can beobserved that for voltages below 10 V, the reflection is not affected bythe switching pulse. When the voltage of the pulse is between 10 V and16 V, the reflection decreases approximately linearly with increasingvoltage. Therefore, a stable gray scale can be obtained in this region.It can be noted that the reflectance of the cell reaches its originalvalue when the voltage is above 30 V.

The other curve, FC-P, shows the switching behaviour of the cell when itwas in the FC state prior to the switching pulse. In this case, thereflectance of the cell is unchanged by the switching pulse ofamplitudes below 22 V. The cell is switched to the P state by voltagesabove 28 V. For both the FC-P and P-FC-P cues, the reflectance contrastbetween the FC and P states is about 20:1. This value is among thebetter values for BCDs as reported in prior literature. The voltagevalues of V₁=10 V, V₂=18 V and V₃=30 V are lower than those reported inprior literature.

Referring now to FIG. 2, this figure shows the temporal behaviour of theswitching from the P to the FC state. The upper curve is the appliedvoltage while the lower curve shows the measure reflectance. It can beobserved from FIG. 2 that switching from the P state to the FC stateoccurs early on in the pulse and is complete in approximately 1 ms.Although the switching time is shown to be 1 ms, the switching pulsecannot be reduced to 1 ms itself as yet. It was found that if theswitching pulse was reduced to 1 ms, the reflectance would rise back upagain. Instead, a holding voltage is needed to stabilize the FC state.As shown in FIG. 2 for this preferred embodiment, the holding voltage isprovided by the 10 ms switching pulse itself.

In the driving scheme of this preferred embodiment, reliance is providedon the column signal to hold the FC state after initial switching by a 1ms pulse. In this example of a multiplex driving scheme, the pixelvoltage consists of the difference between the scanning pulse trainprovided on the horizontal or row electrodes and the data pulse trainprovided on the vertical or column electrodes. As a result, the pixelvoltage will have a noise-like data pulse train together with theselection pulse. These data pulses can be used to hold the FC stateafter the initial switching.

The reflectance of a simulated selected pixel in his preferredembodiment is shown in FIG. 3. It can be seen that the pixel voltageconsists of the initial 20 ms duration ±30 V refresh pulse which setsthe pixel to the P state. This is followed with a 1 ms±30 V switchingpulse which is provided on top of a ±6 V background pulse train. Thisprovides the switching and holding and it can be seen that the switchingfrom the P to FC states is complete with appropriate contrast.

In FIG. 4, a new driving scheme is shown for a binary BCD. Although grayscale is possible from the observed linear nature of the reflectionshown in FIG. 1, the preferred embodiment discussed herein provides asimpler binary BCD. It should be noted that such a gray scale drivingscheme may be provided utilizing this invention.

The preferred driving scheme is shown in FIG. 4. According to thescheme, both the select and non-select pixels will see a 10-20 ms±30 Vpulse in the beginning. This is the reset pulse to refresh the displayto a bright P state. Line by line scanning begins after a 0.1 sdevelopment time. In this multiplexing scheme, a select pixel will seethe sum of the 1 ms address pulse (±24 V) and the data pulse (±6 V). Asa result, the select pixels will see a ±6 V data train together with a 1ms±30 V selection pulse. This will cause the select pixels to switch tothe FC state. In contrast, in the non-select pixel, the data pulsereverses sign. Therefore, the non-select pixels receive the same datatrain plus a 1 ms±18 V pulse. It is important to make sure that, in theparticular embodiment provided, the P state is not affected by thisnon-selection pulse. The voltages are chosen to allow the cumulativeeffect on selected pixels to exceed the threshold for switching to theFC state while the non-selected pixels do not exceed this threshold.

Referring to FIG. 5, this figure shows the influence of the data pulsetrain and the 1 ms±18 V pulse on the P state pixel for this preferredembodiment. It can be seen that the P state remains a P state. However,the reflectance has decreased by about 15%. This generally representsthe cross talk between the select and non-select pixels. Furtheroptimization may be desirable to reduce, this cross talk.

There appears to be a direct correlation between the duration of theswitching pulse, i.e. the addressing speed, and the amount of crosstalk. For long switching pulses, the voltage required for switching fromP to FC states can be reduced. Therefore the P state will be lessaffected by the cross talk.

In a further example, a 2 ms pulse for switching from P to FC states wasused. It was observed that there was a significant reduction in crosstalk in this embodiment. Therefore, the ultimate selection of theaddressing speed can be compromised against the brightness and contrastof the display. It is also noted that in this preferred example, the Pstate appears substantially robust against small voltage perturbationsoccurring during the scanning with 0.5 ms pulses. However, the contrastand brightness are somewhat reduced.

Having scanned the display to select the pixels, this leaves the mattersof the holding time and viewing time in this embodiment. Both arerelated to the last few lines of the panel.

Referring to FIG. 4, a 0.1 s±6 V pulse train is added to the end of thedata pulse train. This is provided to stabilize the FC state for thelast few lines of the panel where the 1 ms 30 V switching pulse appearsat the end of the data pulse train. This holding pulse train can bereduced to 0.05 s in this preferred embodiment if necessary.

The viewing time is also needed for the last few nes of the panel. Thelast few lines of the panel are addressed last and pixel selection willappear at a time later than at the top of the screen. For example, for a100-line display, the time difference is some 0.1 s. Therefore, a longerviewing time may be desirable between frames in order to equalize thebrightness between the first and last parts of the screen to beaddressed. ID most applications of BCDs, the display does not have to berefreshed frequently. This is particularly the case for pagers, cellularphone displays and other such examples. Therefore, the difference of 0.1s or even 1 s for a 1,000-line display does not appear to be asignificant disadvantage.

The apparatus of this preferred embodiment may include a bistablecholesteric liquid display as shown in FIG. 6. FIG. 6 sets out the basicstructure of such a liquid crystal display. Generally such displayscomprise two pieces of glass or similar transparent material 2 betweenwhich the cholesteric liquid crystal material 3 is provided.

On either side of the liquid crystal material, there is provided apatterned electrode layer 5.

In many instances, although not necessary, an alignment layer 4 isprovided on one or both sides of the crystal material.

When incorporated into a full display, a light absorbing black layer maybe provided on the back of the liquid crystal display such as layer 6 inFIG. 6. Although a variety of light absorbing layers may be used,typically ouch layers comprise a layer of black cloth or velvet or evenblack paint or similar,

Referring to FIG. 7, the electrode pattern for a preferred embodiment isshown. The electrode pattern may provide a matrix of electrodes whereinthe electrode layers on both sides of the liquid crystal material form aregular pattern of electrodes. As shown in this example in FIG. 7, anupper layer of electrodes 5A are provided as a series of substantiallyparallel electrodes and the lower layer 5B are again substantiallyparallel and substantially perpendicular to the upper level. The matrixitself provides a series of overlapping regions which may form thepixels of the display.

Although shown as substantially perpendicular rows and colts, theelectrode pattern could be changed to form alternative pixel patternsand displays as desired.

Referring again to FIG. 6, each of the electrode layers receiveselectrical pulses from a suitable pulse generator 7 and 8. The pulsegenerators may be provided by a series of electrical or electroniccomponents. An associated input control or processing means 9 mayprovide the desired signal to the electrical pulse generators 7 and 8 todisplay any particular message.

In general, the voltages provided to each of the row and columnelectrodes are periodic with each period corresponding to one frame ofthe display. Furthermore, the voltages within one frame period asprovided by the drivers are divided into separate phases being the resetphase, data scanning phase and viewing phase.

In such liquid crystal displays, the electrodes 5A and 5B are providedby a transparent conductive film. Again, a number of materials may beutilized although indium tin oxide is common to form the pixilateddisplay.

The optional alignment layer 4 is regularly provided by a coating ofpolymer on the transparent conductive films such that the polymer mayprovide alignment to the cholesteric liquid crystal.

The liquid crystal display cell gap can be chosen to suit the particularapplication. In this preferred embodiment, a cell gap range of 4 to 20μm is sufficient.

It should also be noted that the drivers for the electrodes 7 and 8 mayprovide voltages in each frame period which invert in sign relative toan adjacent frame. The pulses provided may include a reset pulseduration of between 1 to 100 ms in this preferred example and the resetphase duration in this example may be 20 ms to 0.3 s. There is norequirement that the reset pulse duration and reset phase duration bethe same.

The drivers 7 and 8 may provide reset voltages between 10 to 40 V inthis embodiment. This need not be applied to a single electrode layerbut instead may be the result of a reset pulse split between theelectrodes. In any particular example, the reset pulse can be providedentirely on the row electrodes 5B or the column electrodes 5A with zeroV on the other electrode respectively. Alternatively, it may be a resultof a combination of voltages on the electrodes.

The address pulse and data pulse provided by the drivers 7 and 8 in thispreferred example may be in the range of 0.5 to 10 ms in duration. Thiswill provide a display wherein the data scanning phase may be 0.5 to 10ms times the number of row electrodes in duration.

The preferred output of the address pulse voltage is approximately 24±3V and the data pulse voltage is preferably approximately 6±2 V.

It may also be preferable that the row and column voltages may be biasedby the same constant voltage within each frame. This can rest in thesame pixel voltage.

The viewing phase provided in the display may be longer than 0.1 s induration for the preferred embodiment.

Although the time period consisting of the reset phase, data scanningphase and viewing phase can be referred to as periodic, this may not bea regular period. Instead, this may vary as required. As such, theliquid crystal display may be driven only on demand.

Thus it can be seen that this invention provides a method and apparatusfor driving bistable cholesteric liquid crystal displays which, at leastin a preferred form, is capable of 1 ms per line addressing speed. The aaddressing speed may be compromised to reduce cross talk or othermatters according to the particular application. It can utilize soleelectrical wave forms and relies on the faster switching from the P toFC states to provide the faster addressing speed. Although the displayrequires a reset to the P state, the invention may still be particularlyuseful for types of data displays where refreshing is not as frequent.

Specific items mentioned in this disclosure are deemed to incorporateequivalents known to those skill in the art to which the inventionrelates. This scope of the invention is not intended to be restricted bythe described preferred embodiments but instead defined by the appendedclaims.

1. (Canceled)
 2. (Canceled)
 3. (Canceled)
 4. (Canceled)
 5. (Canceled) 6.A bistable cholesteric liquid crystal display comprising: a bistablecholesteric liquid crystal display; a plurality of pixels within saiddisplay; driving means to apply voltage to each pixel; and control meanscontrolling said driving means to supply an initial voltage to saidpixels to set all pixels to the P state, subsequently supplyingsufficient voltage to selected pixels to switch said pixels to the FCstate to provide the desired pattern and maintaining said display for aperiod of time for viewing of the display.
 7. A bistable cholestericliquid crystal display as claimed in claim 6 wherein said displayincludes a matrix of overlapping electrodes with the pixels of thedisplay being defined by overlapping regions of said matrix ofelectrodes.
 8. A bistable cholesteric liquid crystal display as claimedin claim 7 wherein said matrix of overlapping electrodes comprises afirst set of electrodes and a second set of electrodes with the pixelsdefined by the overlapping regions between said first and second sets ofelectrodes and wherein the reset voltage from the driving means isprovided to said electrodes to drive all said pixels to the P state. 9.A bistable cholesteric liquid crystal display as claimed in claim 8wherein the voltage supplied to the pixels for the display comprisesproviding an address voltage to one set of electrodes and a data voltageto the remaining set of electrodes such that selected pixels receive acumulative total of said voltages and non-selected pixels receive a datavoltage of opposite sign to provide a lower total voltage tonon-selected pixels.
 10. A bistable cholesteric liquid crystal displayas claimed in claim 9 wherein said address pulse voltage isapproximately 24+3V.
 11. A bistable cholesteric liquid crystal displayas claimed in claim 9 wherein said data pulse voltage is approximately6+2V.
 12. A bistable cholesteric liquid crystal display as claimed inclaim 6 wherein said electrodes comprise transparent conductive film.13. A bistable cholesteric liquid crystal display as claimed in claim 12wherein said transparent conductive film comprises indium tin oxide. 14.A bistable cholesteric liquid crystal display as claimed in claim 6wherein said liquid crystal cell has a gap of 4 to 20 μm.
 15. A bistablecholesteric liquid crystal display as claimed in claim 6 wherein theliquid crystal display is driven only on receipt of a signal by thecontrol means.
 16. A bistable cholesteric liquid crystal display asclaimed in claim 6 wherein said display is incorporated in a pager orcellular telephone.
 17. A method of driving a bistable cholestericliquid crystal display comprising the steps of: providing a resetvoltage to set the pixels in the display to the reflective P state;switching selected pixels to provide the desired pattern to the FC stateand; holding said display for a suitable viewing period.
 18. a method ofdriving a bistable cholesteric liquid crystal display as claimed inclaimed 17 wherein said method comprises providing electrical pulses tocolumn and row electrodes to impart a voltage on the cholesteric liquidcrystal material in each pixel to drive the switching between the Pstate and the FC state.
 19. A method of driving a bistable cholestericliquid crystal display as claimed in claim 18 wherein said reset voltageis in the range of 10 to 40 V.
 20. A method of driving a bistablecholesteric liquid crystal display as claimed claim 18 wherein said stepof providing electrical pulses to electrodes to switch said selectedpixels to the FC state to provide said display comprises driving one setof electrodes with an address pulse and the remaining set of electrodeswith data pulses such that the selected pixels are subjected to avoltage being the sum of the address and data pulses which is greaterthan the threshold voltage to switch to the FC state and thenon-selected pixels receive a voltage with a data pulse of inverse signat a voltage below the threshold for switching to the FC state.
 21. Amethod of driving a bistable cholesteric liquid crystal display asclaimed in claim 18 wherein said viewing phase comprises applyinginsufficient voltages to any pixels to cause a change from the P stateto the FC state.